jarat munaqashat talibat almajistir (nuras husayn eabdallah) min qism handasat alhasub ean risalatiha almawsumati:

"Memristive Hardware-Based Architecture Authenticated Encryption Using FPGA"

wadhalik ealaa qaeat majlis qism handasat alhasub min yawm alahid almasadif 16/4/2023

wata'alafat lajnat almunaqashat min alsaadat almudrajat 'asmawuhum 'adnahi:

'a.mu.da. bilal rashid eabdalmijid/jamieat alshaebu/kiliat alhandasat watiknulujia almelwmat.ryysaan

'u.mu.da. lahib muhamad jawadi/ jamieat alnahrini/kiliat handasat almelwmat.edwaan

mu.da. raslan saed eabdalrahmin/jameat alnahrayn /kaliyat alhnds.edwaan

mu.du. asara' badr nasir/jamieat alnahrayn /kuliyat alhnds.mshrfa

alaihdafi: tatadaman aihdaf albahth ainsha' miemariat altashfir almusadiq lilajihazat alqayimat ealaa tiqniat almimristur nanutiknuluji bi'ustikhdam albawaabat almantiqiat alqabilat lilbarmaja

waqad listufit altaalibat mutatalabat alhusul ealaa shahadat almajistir  binajah

Internet of Things (IoT) connects various devices through the network such as smart devices, radio frequency identification tags, and sensors. Sharing sensitive information and private data between these devices needs to provide a secure communication path and safe access. Most of these devices have limited resources including memory, size, speed, and power, which will require ultra-low power consumption devices and lightweight cryptographic algorithms. Memristor, a novel nanotechnology device is embedded in hardware security applications because of its unique electrical response. Memristor’s electrical response displays a hysteresis loop that is pinched in the current-voltage (I-V) plane. As a result, a specific mathematical model finds it challenging to forecast the behavior of individual memristor devices.

This work presents a new hardware security module (HSM) involving memristive key generation relays mainly on the unique behavior of the memristor's I-V characteristics. The generated memristor-based secret key has been utilized in the hardware implementation of a lightweight authenticated encryption scheme, which is based on the ANU-II block cipher algorithm and PHOTON hash function. The latency is equal to 16, 13, and 36 clock cycles for the memristive key generation, ANU-II block cipher, and PHOTON hash function, respectively. Two authenticated encryption data path approaches were implemented: Encrypt-then-Mac (EtM) and Mac-then-Encrypt (MtE). The latency of the EtM is a 65-clock cycle, while the latency of the MtE is 123 clock cycles.

The proposed design shows high throughput and efficiency. A throughput of 533.089, 482.796, 643.771, 702.068, 226.036, and 323.143 Mbps and efficiency of 0.6959, 0.6696, 0.8929, 0.9737, 0.3018, and 0.4445 Mbps/slice have been obtained when implementing the proposed design on Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-3 and Spartan-6, respectively. Also, the proposed work achieved low power consumption equal to 1618, 3542, 3447, 177, 338, and 117 mW when implemented on Virtex-4, Virtex-5, Virtex-6, Virtex-7 Spartan-3, and Spartan-6 FPGA platforms, respectively. Where lower power consumption is achieved on both Spartan-6 and Virtex-7 platforms.